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msm8974 parts fall into multiple bins with different voltage
requirement. Until now, software used conservatively high
voltages to support all parts. Introduce PVS voltages tables
so that lower voltages can be selected based on the PVS bin.

Change-Id: I70d474ae42df515a538a01e559d8d11e92ed4e0b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

msm8974 and future targets use a different eFuse register layout
than targets from previous SoC generations. Instead of hard-coding
acpuclock-krait to assume the old format, allow the format to
be decided on a per-SoC basis via function pointer assignments.

Two formats are currently supported:
 - "Format A", used for 8974
 - "Format B", used for older Krait-based targets

Change-Id: Id9e8a6c83e3003f2b19ac56bb7aee5dc6b1d00cf
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The L2 parity errors observed at middle L2 performance points have
been resolved in newer silicon revisions. Apply the workaround only
to the affected revisions.

Change-Id: I7baab92fbb8340e59071f3cd82696f7352714ca1
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Tests have shown that entering pfm mode when there is more than one
cpu running at 300Mhz causes instability.

Update the current required at 300Mhz to 400mA so that pfm mode is
entered only when one cpu is online and is running at 300Mhz.

This 400mA is a temporary placeholder and will be a updated when
HW is characterized.

Change-Id: I93d5630ff9e797c981db3d64c5d71097dba9f3fc
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

This reverts commit 335bc46d

.

The revert of the acpuclock table to lower voltages did indeed
improve stability, but was not the underlying root cause of the
reported failures.

It turns out that a hardware bug prevented the PMIC regulator
MODE_CTL register from being reset in WARM_RESET. Consequently,
we often left the regulator running in PFM mode. This is bad,
since our software assumes the default value is PWM. Thus we
would often end up bringing up cores at higher current
requests than that tolerated in PFM mode, and crash the system.

Change-Id: Ie8b1ccef10577aceaa5201ec67dd220dcd87c210
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>

Memory is now able to run up to 800MHz, and has updated performance
levels for the lower rates. Update the driver data accordingly.

As a result of this change, memory will now run at 800MHz whenever
the L2 is running at 1.5GHz, up from 556MHz which was previously
used.

Change-Id: I5b1ed868d4e15bd56562c19fa51020983561323e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Recently, CPU voltages were decreased and their maximum frequency
increased as part of c1f139c4

. Since
that time, some devices have been experiencing higher crash rates,
with symptoms similar to those expected from an under-volted CPU.

Revert back to more conservative CPU performance levels until this
these stability issues have been resolved.

CRs-Fixed: 428134
Change-Id: I956069ef19c7ae82abf14133c006bab0772e9550
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The RPM processor manages the dependency between the PM8941
SMPS 2 and LDO 12 regulators on MSM8974 targets.  Therefore,
remove the usage of pm8941_s2 in both the MSM8974 device tree
as well as the acpuclock-8974 driver.  The enable requests made
for pm8941_l12 will be propagated to the S2 regulator by the RPM.
Removing the usage of pm8941_s2 means that redundant S2 regulator
requests will not be sent to the RPM.  This will reduce the
latency of some acpuclock operations.

Change-Id: Ib91a750bb3c224516d036c67c37ab586592bb3d4
Signed-off-by: David Collins <collinsd@codeaurora.org>

Most of the CPU and L2 HFPLL performance levels are spaced evenly
by 76.8MHz, with the exception of a couple at the bottom of the
table. Update these so the table is more linear and matches the
levels that are used for chip characterization.

Also, clear the use_for_scaling flag for a few intermediate levels
that share the same Krait voltage. These frequency steps do not
provide a significant power advantage over their neighboring steps
and can therefore be omitted.

Change-Id: I64ef9c31ff319c929b75a5e2c4a7a3b8334e62dd
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Preliminary hardware characterization data is available which shows
voltages may be safely decreased to the levels applied in this patch.
Additionally, the maximum CPU speed can be increased to 1728MHz.

Future characterization may allow voltages to be decreased further;
safe values are used for now.

Change-Id: I09bed11e114406aa9e199cfbd0e52880f9ccc849
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Frequency and voltage sensitivities in some of these early revision
parts cause L2 parity errors to be observed at different frequency
and voltage combinations. 300MHz and 1.5GHz with vdd_mx at 1.05V,
however, is shown to be reliable across all parts.

Restrict L2 scaling to these two performance points for now. This
restriction will be removed for future silicon revisions.

CRs-Fixed: 407593
Change-Id: Ib3eba2f493975a84e7be2067a076f99f86f1246c
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

For the lowest frequency the cpu may not need 3.2Amps.
Use a lower value, 100mA, to avail the pfm mode savings.
Note that this 100mA is a temporary placeholder and will
be a updated when HW is characterized.

Change-Id: I21a8c7775282369a0583b3b35e554daa03acb516
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Add support for 1.7 GHz and 2.0 GHz parts and their corresponding
L2 and memory bandwidth votes.

Support selecting different PVS tables based upon EFUSE speed bin
across all krait targets.

Change-Id: Ibbf6b5182fce0a9e92014883d07a35dee5f0d2a1
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

With use of the QSB clock source recently eliminated, only one
input of the secondary clock MUX is used on any target. Since
there is overhead involved reprogramming this MUX when changing
the CPU and L2 frequencies, change the code to just program the
MUX at boot.  Most noticeably, this removes a 1us delay from
every CPU and L2 frequency switch.

Change-Id: I5cd8c981f1be49be7dbba1310d84df439e8be83b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

This mask is needed in order to switch VCO modes when running the
PLL at frequencies above 1700MHz. Specify the missing data. Because
rates about 1.7GHz are not used yet, the missing mask should not
have been the source of any real problems.

Also remove the TODO line that was inserted as a reminder to
double-check the 'magic' PLL configuration register values after
hardware characterization. That has since been done and the
original values were determined to be fine.

Change-Id: I548c02e44cc5fded740e513252110e7318fec6e8
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Correct the efuse address base and offset for 8974. Since the offset
is now different on 8974 than on other Krait-based targets, it's no
longer possible to hard-code it in acpuclock-krait.c. Instead, move
it into the QFPROM address passed from SoC specific files.

Since the PTE EFUSE is not yet used on 8974 to select different
frequency/voltage tables, this change should have no current
functional effect.

Change-Id: I26de7c9ce84e2873b883123f9fe420b3cb14e364
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

find_cur_l2_level() assumes that the L2 table is NULL terminated
when it has never been terminated. Therefore, if the rate that is
read from the hardware during boot is not found in the table we
will run off the end of the table and read potential junk values.
NULL terminate all the L2 tables so that the loop in
find_cur_l2_level() is guaranteed to terminate.

Change-Id: Ia5d0213000b44def35e388fd3cadf0293344257b
Reported-by: Laura Abbot <lauraa@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

Devices appear stable at these increased rates, even on early
hardware. Raise the frequency limit from 1.0GHz to 1.5GHz.

Change-Id: Ic0b5e8193a94d39c53721350b966656d5f734e33
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Update the performance levels per the latest clock plan. Voltages
remain conservatively high until hardware characterization is done.
For similar reasons, the max frequency for the CPUs is limited to
1036.8MHz, and the max for the L2 cache to 806.4MHz.

Change-Id: I0909a8c0e060715c4c8eaa0ec43bbe9dd7eaf72f
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

QSB's rate is tied to the Apps fabric (or BIMC on 8974), which means
that its rate is unpredictable. When the CPU is running at a low
voltage, if the QSB clock source is selected, it's possible that the
CPU clock rate could increase beyond the safe limit for that voltage.

Instead of selecting QSB for power-collapse and hotplug scenarios,
select an always-on source with a predictable rate.

Change-Id: I7c39d443bf49371358d0a618693a6efe2f26fcc4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Updated hardware recommendations have been released. Capture these.
Although the voltage requirements are higher than was previously
specified, this is not expected to affect actual voltage levels
because the vdd_dig requirements of the of the L2 cache (as
enforced by acpuclock) are already higher than the new HFPLL
requirements.

Change-Id: I4087b35f07276d063d09756067ce7166093f65dc
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The HFPLL configuration recommended by the hardware designers has been
updated. Update acpuclock to match.

In addition to changes to the static register configuration, runtime
selection of the correct VCO mode is required. For frequencies above
1248MHz, the high-frequency VCO mode is used. The low-frequency mode
is used for frequencies below that.

Change-Id: Ib0585b5262d27791128a54910b75d2dc0c581775
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The current acpuclock-krait driver asserts a constant regulator
current request when a CPU is initialized or inserted, and
removes it when a CPU is hotplug-removed.

Improve on this by allowing the current requests to scale based
on the speed of the CPUs. This allows acpuclock drivers to
factor dynamic power into its current requests, which will
change based on the frequency.

Only msm8974 regulators support current requests, so the cur_ua
column is omitted from the other frequency tables. The 8974
table is populated with pessimistic placeholder currents for now,
until characterization data is available.

Change-Id: I1ef89406a0de0038d32039c361b755a5eedba847
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The HFPLL data for the CPU PLLs and the L2 PLL are the same with the
exception of the voltage data specified. The voltage data, however,
is only relevant for the L2 PLLs (since the CPU HFPLL voltage
requirements are captured as part of the CPU frequency/voltage table).
Because of this the tables can be combined.

Change-Id: Ic8c9bdcf3c3c32a62906031fe5ffbc60a8b824f4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Refactor the initialization code so that datastructures that must be
kept are kmemduped and the rest are discarded after the kernel has
booted with the help of __initdata markings.

For a typically-compiled all-in-one kernel containing support for
msm8960, apq8064, msm8627 and msm8930, this allows 11.5K to be moved
from the .data to the .init.data section, with less than 10% of that
retained in dynamically-allocated memory (the exact amount varies
depending on the device the kernel is booted on).

Change-Id: I505eef8f10dc0e44bab15954b797252c3c408e50
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

By referencing L2 frequency table rows by indexes rather than pointers,
we allow for future enhancements which will allocate the L2 frequency
table at runtime.

Change-Id: Icc62962d5d7b27dbf39008bc6eff83c4ee8951c4
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Update the placeholder/conservative voltage data to allow vdd_dig to
drop to SVS levels when the L2 is running at its slowest. The values
will be updated again when real data is available.

Change-Id: I483865261354e1f397238cfb165d0389c1fd2102
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

PM8941_S2 is the parent of PM8941_L12, which supplies the HFPLLs.
Because the rpm_regulator_*() APIs do not manage this relationship,
it is necessary to enable both from acpuclock when the HFPLLs are
needed.

Change-Id: I1f60934f1cdfc7acfdf3dec5a793754896c8d33f
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

New voltage corner enums have been introduced in the RPM regulator
driver for msm8974's vdd_dig rail. Update acpuclock accordingly.

Change-Id: Id4d316b25cdc61d7a0ee330f6423f242881fca0b
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The official name for copper is MSM8974.
Switch to it.

Change-Id: Ifb241232111139912477bf7b5f2e9cf5d38d0f9e
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

Support for rpm_vreg_set_voltage is not supported on newer targets like
msm-copper. It has been replaced by the rpm_regulator_*() family of
APIs. Update acpuclock-krait accordingly.

Change-Id: I980aeff025f15239b2ecf11133afd770ee13bba1
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Add a new generic acpuclock driver for Krait CPUs, along with msm-copper
specific configuration data. This is a generalization of the existing
acpuclock-8960 driver, which it is intended to eventually replace. A
library of core driver code exists in acpuclock-krait.c with target-
specific data living in acpuclock-copper.c (and, eventually, other
similarly-named files).

Unlike existing acpuclock drivers, acpuclock-copper is a platform driver
with a platform device defined in a device tree. The driver probes when
the platform device has been registered and platform_driver_probe() has
been called in acpuclock-copper's device initcall.

Change-Id: I334ed0e215bb4076461f7bc39cf4ec89dbc35a8e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>