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Most of the CPU and L2 HFPLL performance levels are spaced evenly
by 76.8MHz, with the exception of a couple at the bottom of the
table. Update these so the table is more linear and matches the
levels that are used for chip characterization.

Also, clear the use_for_scaling flag for a few intermediate levels
that share the same Krait voltage. These frequency steps do not
provide a significant power advantage over their neighboring steps
and can therefore be omitted.

Change-Id: I64ef9c31ff319c929b75a5e2c4a7a3b8334e62dd
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>