1. 06 Feb, 2013 2 commits
  2. 05 Feb, 2013 3 commits
    • Anirudh Ghayal's avatar
      power: pm8921-bms: Enable batt alarm · 6fe4ffa6
      Anirudh Ghayal authored
      
      Set the batt alarm to wake up the system if the
      battery voltage falls below a threshold. This is to
      make sure that the device does not shutdown abruptly
      without any notification.
      
      Hold the low voltage wakelock to prevent the device
      from going to sleep immediately after the low voltage
      notification.
      
      Change-Id: Ifaeeeb27bd85f9c95f026ac3565681432e247b02
      Signed-off-by: default avatarAnirudh Ghayal <aghayal@codeaurora.org>
      6fe4ffa6
    • Tianyi Gou's avatar
      msm: acpuclock-8930ab: Lower VDD_DIG voltage vote for L2 at 384MHz · f684b386
      Tianyi Gou authored
      
      New characterization data shows that vdd_dig voltage for L2@384MHz
      can be lowered to the low level. Update the data in this patch.
      
      Change-Id: Ia80ee9397b3b433b96f2bce49a86d5ef7b024fc5
      Signed-off-by: default avatarTianyi Gou <tgou@codeaurora.org>
      f684b386
    • Sriranjan Srikantam's avatar
      msm: audio: qdsp5: Add support of dynamic re-enable of post proc · 87a6c295
      Sriranjan Srikantam authored
      
      DSP can disable the post processing features due to unavailability
      of MIPS during video playback. As a result difference in audio
      quality is observed after video playback. Add support to re-enable
      the post processing features once video playback ends and MIPS are
      available.
      DSP sends a message whenever post processing features are disabled
      due to unavailability of MIPS and sends another message once the
      MIPS are available. AUDPP driver broadcasts these messages to all
      the relavant clients which keeps track of disabled features and
      re-enables them when re-enable message is received from DSP.
      
      Change-Id: Ic4cad4e7b0afe4377006055417ba193b01cce930
      Signed-off-by: default avatarSriranjan Srikantam <cssrika@codeaurora.org>
      87a6c295
  3. 04 Feb, 2013 1 commit
  4. 01 Feb, 2013 3 commits
  5. 31 Jan, 2013 2 commits
  6. 30 Jan, 2013 4 commits
  7. 28 Jan, 2013 1 commit
  8. 26 Jan, 2013 1 commit
  9. 25 Jan, 2013 3 commits
  10. 24 Jan, 2013 10 commits
  11. 23 Jan, 2013 2 commits
  12. 22 Jan, 2013 2 commits
  13. 21 Jan, 2013 5 commits
    • Abhimanyu Kapur's avatar
      arm/dt: 9625: Add dt support for MDM9625-V2 · 2a74a928
      Abhimanyu Kapur authored
      
      Create new dts files for various board types supporting
      the MDM9625-V2 chipset.
      
      Change-Id: I91d6553ce751ec4d17cddb44e245fde96534e545
      Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
      2a74a928
    • Abhimanyu Kapur's avatar
      arm/dt: 9625: Rename DTS files to include SoC version · 7ef42bed
      Abhimanyu Kapur authored
      
      Include the SoC version in the file name of the MDM9625v1
      DTS files in preparation for adding the equivalent files
      for MDM9625v2.
      
      Change-Id: Ifa1cffb38d4cbead3d662e3b257ff8a92a7f2b37
      Signed-off-by: default avatarAbhimanyu Kapur <abhimany@codeaurora.org>
      7ef42bed
    • Saravana Kannan's avatar
      msm: clock: Improve clock handoff code. · c85ecf90
      Saravana Kannan authored
      
      The current clock handoff code hands off the child clock before handing off
      the parent clock. That is technically incorrect since the state and rate of
      a clock can't be determined without knowing the state and rate of the
      source/parent clock. But this works alright for now since the handoff code
      forcefully enables the necessary parent and also assumes that if a clock
      has multiple parents, the rates of all those parents are fixed. As we
      implement more clocks, this assumption no longer holds true.
      
      The current handoff code also causes the prepare and enable ops to be
      called for an already enabled clock. The hardware read/writes caused by
      this might not be harmful in the case of most clock hardware designs, but
      is not always the case. Eg: PLLs, I2C clocks, etc.
      
      To address these issues, rewrite the clock handoff code so that the parent
      clock is identified first, it's handed off and then the child clock is
      handed off. Also, when an already enabled clock is handed off, just
      directly update the software state of the clock and don't call the ops to
      update the hardware. To make sure the parent clock's reference counts are
      updated correctly, call clk_prepare_enable() on the parent clock.
      
      This change also has the nice effect of avoiding any "clock stuck off/on"
      warnings during boot that are caused by the boot code configuring the
      clocks incorrectly (parent off, child on). This is because we don't
      actually call the prepare/enable ops and also make sure the parent clocks
      is on before calling the handoff code for the child clock.
      
      Change-Id: I385a2afaf62a4138d53048f675822e079be2fcca
      Signed-off-by: default avatarSaravana Kannan <skannan@codeaurora.org>
      c85ecf90
    • Gagan Mac's avatar
      msm: msm_bus: Correct bypass mode settings for BIMC masters · 62aa8807
      Gagan Mac authored
      
      If a master is in fixed or bypass mode, it's bandwidth registers
      should not be touched. Currently, the bus driver attempts to
      configure bandwidth registers during init. This patch fixes
      this error.
      
      Change-Id: I49b2104f1c429ac5ea3fb4e8f692cb3dd363c3be
      CRs-Fixed: 439869
      Signed-off-by: default avatarGagan Mac <gmac@codeaurora.org>
      62aa8807
    • Eric Holmberg's avatar
      msm: smem: Add new SMEM items · 6be19c23
      Eric Holmberg authored
      
      Add new SMEM item definitions for BAM PIPE memory and software image
      versions.
      
      Change-Id: Iee7dade741476a83a788441a1f18942fff4cfa86
      Signed-off-by: default avatarEric Holmberg <eholmber@codeaurora.org>
      6be19c23
  14. 20 Jan, 2013 1 commit
    • Taniya Das's avatar
      msm: mdm2: Add delay between subsequent PS_HOLD · 2b7646be
      Taniya Das authored
      
      During SSR first a reset of external modem is issued
      and mdm_do_soft_power_on() toggles ap2mdm_soft_reset which
      in turn toogles the PS_HOLD. Then a part of SSR external
      modem is powered up and mdm_do_soft_power_on() again toggles
      the gpio. For PMIC register stabilization we need a 1sec delay
      between subsequent mdm_do_soft_power_on().
      By default the delay is 500msec, so adding another 500msec for
      stablization.
      
      Change-Id: I928c064f386c1e376fc5b0740c2d1336f549398f
      Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
      2b7646be