GitLab

The voltage of vdd_dig is specified using the corner level values. Fix
the use of the max vdd to be the level values instead of the concrete
voltage number.

Change-Id: I10fa63c70af1d6510f9378ec7529ad00930e4cfa
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

Debug logs dumped by SDI are not available if a watchdog reset occurs
after a kernel panic. Add support for these logs to be available.

Change-Id: If6ebf44b6205399599a6bff48d422908e37304c3
Signed-off-by: Pushkar Joshi <pushkarj@codeaurora.org>

Set the batt alarm to wake up the system if the
battery voltage falls below a threshold. This is to
make sure that the device does not shutdown abruptly
without any notification.

Hold the low voltage wakelock to prevent the device
from going to sleep immediately after the low voltage
notification.

Change-Id: Ifaeeeb27bd85f9c95f026ac3565681432e247b02
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>

New characterization data shows that vdd_dig voltage for L2@384MHz
can be lowered to the low level. Update the data in this patch.

Change-Id: Ia80ee9397b3b433b96f2bce49a86d5ef7b024fc5
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

DSP can disable the post processing features due to unavailability
of MIPS during video playback. As a result difference in audio
quality is observed after video playback. Add support to re-enable
the post processing features once video playback ends and MIPS are
available.
DSP sends a message whenever post processing features are disabled
due to unavailability of MIPS and sends another message once the
MIPS are available. AUDPP driver broadcasts these messages to all
the relavant clients which keeps track of disabled features and
re-enables them when re-enable message is received from DSP.

Change-Id: Ic4cad4e7b0afe4377006055417ba193b01cce930
Signed-off-by: Sriranjan Srikantam <cssrika@codeaurora.org>

vreg_n is needed in pcie platform data because of the recent change -
"msm: pcie: add support for MPQ8064 Hybrid"

Change-Id: I481d7a9bd774484b48a64897f231a2f864a582fe
Acked-by: Kaushik Sikdar <ksikdar@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

If an inbound entry changes, both the inbound and outbound entry locks
are held while performing an interrupt notification.  If a client then
attempts to set a new outbound bit in the notification function, then a
deadlock will occur.

Verify that the outbound entry is open (which is a terminal state) and
then unlock the outbound spinlock before doing the notification.

Change-Id: I662b721ef5fd48e75d12019bf12e370f4a7eea9d
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>

Voice host pcm feature allows userspace to tap out and inject
PCM samples into the voice topology using shared memory.
Add platform data for voice host pcm.

Change-Id: Ie277293f2af98679c084e0fceba36047d85fa305
Signed-off-by: Shiv Maliyappanahalli <smaliyap@codeaurora.org>

Add the SMEM_LC_DEBUGGER smem item definition to support the low cost
debugger feature.

Change-Id: I4d39b8fa4179709c860596cd8b74d6597519fede
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>

Reading the current value of TSIF clock reference counter
is required by some application.

Change-Id: I0fceb46ee50b8c76674ea9b8169e0b31f63fba3d
Signed-off-by: Hamad Kadmany <hkadmany@codeaurora.org>

Add support for soft volume command and enable it to avoid
noise during volume change sequence.
Add support for soft pause command and enable it to avoid
noise during pause/resume change sequence.

CRs-Fixed: 425431
Change-Id: Ie10c73a0f35a191168f4306b1122102ed0f75ad0
Signed-off-by: Deepa Madiregama <dmadireg@codeaurora.org>

PCIe has different GPIO numbers and regulator numbers on MPQ8064
Hybrid. Add the support for PCIe on MPQ8064 Hybrid.

Change-Id: Ib2edf0f67ef118290587e581cdddd3ce66cd2920
Signed-off-by: Yan He <yanhe@codeaurora.org>

PCIe has different regulator numbers on various MPQ8064 platforms.
Add the support in PCIe driver for various platforms.

Change-Id: Ib2662f4cba04ce4de9cce18d4b8e4682a04a276e
Signed-off-by: Yan He <yanhe@codeaurora.org>

Time stamp is unsigned. There is no need to check for
negative value.

Change-Id: Ibd163a43cdfdb056e6ed775799fb709def9733df
CRs-fixed: 423372
Signed-off-by: Patrick Lai <plai@codeaurora.org>

Currently, the CP heap supports non-secure allocations as long as the
no_nonsecure_alloc flag is not set in the device tree or platform data
for the heap. Since allowing non-secure allocations from secure heaps
is actually the exception rather than the rule, remove this flag and
replace it with a flag that can be set to accomplish the inverse
(i.e. override the policy of disallowing non-secure allocations from
secure heaps).

Change-Id: I1d03991a895c3cf2dea67f79d6af0d4244fb5a75
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>

MDM8225 and MDM9230 represent modem variants of the
MDM9625 chipset. Add support for them.

Change-Id: I5289fe4a530e34eff2bb1668df54eb450aa87494
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

Move IMEM initialization from iomap header file to
device tree for supported targets.

Change-Id: I6a375df45d88f79327a977c43d2c31f00d1a64b8
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

Certain 8960ab devices have a graphics core capable of running at 440MHz.
These devices are distinguished from regular 8960ab devices through a
speed bin attribute located in efuse.

Configure PLL3 to provide 880 Mhz, which is divided down to the rate
graphics requires.

Change-Id: I9d9e8d52bff1345809450dc24ef55667f7317775
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

This change adds UART1 clock configuration to use
BLSP1 based UART1.

Change-Id: Ice674e45cd8f86f6b10e6f8a9ddabe74cc165757
Signed-off-by: Saket Saurabh <ssaurabh@codeaurora.org>

Correct the copyright information from CAF to The Linux Foundation

Change-Id: I2d0723c3bc8659bfc326b55b12b5cfa30b2a9bfb
Signed-off-by: Devendra Patel <cdevenp@codeaurora.org>

On 9625v2, new RCG sources are added for QUP I2C clocks.
Add support for these sources.

Change-Id: I904334c9a6f6e77db13b9bd94061b0872a529ade
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

If an SMP2P entry is changed while version negotiation is ongoing, then
only an OPEN event will be sent instead of the expected OPEN event
followed by an UPDATE event.

Modify the code to always send an OPEN event followed by an update event
for this case.

Change-Id: Ideba72346d40679eab3c21da4ae24d26f0dfaace
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>

All pointers to SMEM should be delcared with the __iomem tag to aid in
static analysis and to indicate to developers that they should use iomem
access functions such as readl() and writel() to access the memory.

Change-Id: If784ea86caa8d95943bec23d6dffb85643981b06
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>

Assign new fmax tables instead of overriding individual fmax entries
to both mdp and gfx3d clocks.
Merge two similar frequency tables for the mdp clk.

Change-Id: I2462e0898a529944f1ab9aea3055d49b91a5f4ae
Signed-off-by: Patrick Daly <pdaly@codeaurora.org>

QDSS bam connection number is different on different targets.
This change implements configurable setting
of qdss bam connection number.

Change-Id: Ib220673b1454e23f1b15ddd47b0d448445af0a17
Signed-off-by: Anna Perel <aperel@codeaurora.org>

Add PM8921 GPIO initialization configurations in order to
support PCIE and USB ports on the Femto development target
(FDP).

Change-Id: I0a1b8b536edf71387be2e27465585e0567efb71a
Acked-by: Jie Luo <jluo@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Femto development platform (FDP) has a slighly different
layout than the CDP.

Change-Id: I165b585cb9676c0b8cbcfe1dd170f654cdada7d5
Acked-by: Kaushik Sikdar <ksikdar@qti.qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Make sure dev pointer is not NULL before accessing it.

Change-Id: I1808d166c1eefd4f17be13d5252c0fcd0ec86c80
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>

Modify the Comparison of unsigned value against 0 as it is
always false.

Change-Id: I5278b1fa5d89df09910b405610635642686294a6
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>

MVS driver closes the RPC endpoint while it sends reply to the
RPC read sometimes. The RPC write for this reply results in
crash as endpoint is already closed.
Wait for RPC read and reply to complete before closing the
endpoint.

CRs-Fixed: 443706
Change-Id: Ia1918082118f23ab9aefec1c3a04908d8d8c1199
Signed-off-by: Sriranjan Srikantam <cssrika@codeaurora.org>

Do not allow the GPU to go into SLUMBER while the display is still
on. This fixes issues seen on 8930 when this feature is enabled.

Change-Id: I8c76d1297c2215987bdd493cb9f04d45d9ec87dc
Signed-off-by: Lynus Vaz <lvaz@codeaurora.org>

From 9625v2, the hardware adds the measurement support for ipa and
qpic clocks. Therefore, add this support in clock driver as well.

Change-Id: Ib4576bff31431a694ad2159183b8a097416f27fe
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>

Define primary default LPM configurations in Kconfig for 8610.
Compile pm-8x60, cpuidle, rpm, spm and mpm drivers for 8610.

Change-Id: Iad3026b8607480f5fe1ed20c39837519a61a6832
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>

Initialize drivers that need ordering separetely and before the
devicetree initialization. LPM and RPM drivers have ordering
requirements and may be needed by other drivers that are initialized
by platform device.

Also update the init_irq function to initialize MPM.

Change-Id: If7ed790a72dca74089044c7d4722d071bd1f932a
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>

Create new dts files for various board types supporting
the MDM9625-V2 chipset.

Change-Id: I91d6553ce751ec4d17cddb44e245fde96534e545
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

Include the SoC version in the file name of the MDM9625v1
DTS files in preparation for adding the equivalent files
for MDM9625v2.

Change-Id: Ifa1cffb38d4cbead3d662e3b257ff8a92a7f2b37
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

The current clock handoff code hands off the child clock before handing off
the parent clock. That is technically incorrect since the state and rate of
a clock can't be determined without knowing the state and rate of the
source/parent clock. But this works alright for now since the handoff code
forcefully enables the necessary parent and also assumes that if a clock
has multiple parents, the rates of all those parents are fixed. As we
implement more clocks, this assumption no longer holds true.

The current handoff code also causes the prepare and enable ops to be
called for an already enabled clock. The hardware read/writes caused by
this might not be harmful in the case of most clock hardware designs, but
is not always the case. Eg: PLLs, I2C clocks, etc.

To address these issues, rewrite the clock handoff code so that the parent
clock is identified first, it's handed off and then the child clock is
handed off. Also, when an already enabled clock is handed off, just
directly update the software state of the clock and don't call the ops to
update the hardware. To make sure the parent clock's reference counts are
updated correctly, call clk_prepare_enable() on the parent clock.

This change also has the nice effect of avoiding any "clock stuck off/on"
warnings during boot that are caused by the boot code configuring the
clocks incorrectly (parent off, child on). This is because we don't
actually call the prepare/enable ops and also make sure the parent clocks
is on before calling the handoff code for the child clock.

Change-Id: I385a2afaf62a4138d53048f675822e079be2fcca
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>

If a master is in fixed or bypass mode, it's bandwidth registers
should not be touched. Currently, the bus driver attempts to
configure bandwidth registers during init. This patch fixes
this error.

Change-Id: I49b2104f1c429ac5ea3fb4e8f692cb3dd363c3be
CRs-Fixed: 439869
Signed-off-by: Gagan Mac <gmac@codeaurora.org>

Add new SMEM item definitions for BAM PIPE memory and software image
versions.

Change-Id: Iee7dade741476a83a788441a1f18942fff4cfa86
Signed-off-by: Eric Holmberg <eholmber@codeaurora.org>

During SSR first a reset of external modem is issued
and mdm_do_soft_power_on() toggles ap2mdm_soft_reset which
in turn toogles the PS_HOLD. Then a part of SSR external
modem is powered up and mdm_do_soft_power_on() again toggles
the gpio. For PMIC register stabilization we need a 1sec delay
between subsequent mdm_do_soft_power_on().
By default the delay is 500msec, so adding another 500msec for
stablization.

Change-Id: I928c064f386c1e376fc5b0740c2d1336f549398f
Signed-off-by: Taniya Das <tdas@codeaurora.org>