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SEC MI2S GPIO are shared with SDC3 on MDM9625.
Reverting secondary MI2S GPIO installation for
MDM9625.

Change-Id: I7728daf276b622ee37a85c9cf40b36cf15654818
Signed-off-by: Venkat Sudhir <vsudhir@codeaurora.org>

Add support for secondary MI2S interface in qdsp6v2
cpu driver. Secondary MI2S block in ADSP will be
configured for audio purpose.

Change-Id: I930548e3abc2fafc5ab8d853fb2b92cc1c60b026
Signed-off-by: Venkat Sudhir <vsudhir@codeaurora.org>

Remove the use and definition of the NR_GPIO_IRQS macro for
device tree targets. This involves removing the macro from the
gpio driver as well. Since this a common gpio driver, certain
non-device tree targets had to be fixed to support this.
However, the NR_GPIO_IRQS macro continues to exist for the
non-device tree targets.

Change-Id: Ie05b20e9f7732f3eb9c972d2aa81280f4b736f29
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Install gpiomux settings for SDC2 card detection.

Change-Id: I242165c071b4ea89985c8ece5cb58e4200409e32
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>

Add gpio configurations for MDM9x25 to use I2S
interface with codec. Install codec reset
gpio configurations. I2S interface uses these
gpio for clock , data.

Change-Id: I1290b0648e1bb1a0139e8df954db3b773402474c
Signed-off-by: Venkat Sudhir <vsudhir@codeaurora.org>

Platform-data has the following misconfiguration:
1.Clock frequency: Device-Tree entries specify frequencies that
  are not present in the clock frequency table.
2.Bus-number: Missing bus-number specification in the Device-Tree
3.Clock lookup table: Pre-Device-Tree SPI device name in the
  clock lookup table.
4.Redundant aux-data entry:  Pre-Device-Tree aux-data entry in
  the board-file.
5.GPIOs: GPIOs are set to wrong number and function.
6.QUP: Wrong QUP numberand corresponding address and interrupt.

This patch updates and fixes the above items. It sets the clock
rate to the nearest lower frequency that is present in the clock
frequency table.

Change-Id: I31a71cc31d7d2f1b365638d4e8aa07bbaec316b9
Signed-off-by: Gilad Avidov <gavidov@codeaurora.org>

Update the gpiomux settings for AR6004 CHIP_PWD_L gpio pin.

Change-Id: I699f6f1a6be4caad7058d0328100e7562fe2bec7
Signed-off-by: Pavan Kumar <pavan@codeaurora.org>

Add gpiomux settings so that MSM9625 GPIOs 10 and 11 are
configured for use with the I2C core BLSP1 QUP3.

Change-Id: I3b783055e503e2718652a9fa5b0952daa12819eb
Signed-off-by: David Collins <collinsd@codeaurora.org>

Add device tree bindings, clock and gpiomux
entries for SDC3 SDIO slot with support for
DDR50 mode (100MHz).

Change-Id: I01d4ba4b97030451dd68066df29e0fe0eb441429
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>

Update the UART rx and tx gpio pins according to TLMM IO map.

Change-Id: I32cec8e3af2da090e2bd6d0ac4c6c986457d17cb
Signed-off-by: Abhimanyu Kapur <abhimany@codeaurora.org>

9625 supports SPI ethernet on BLSP1 QUP6. Add the dts data,
gpiomux configurations and the board setup code for it.

Change-Id: Ib185a9a0a6bf830fcb53b05a2c60e34a740e8e52
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Add the MSM9615 gpiomux configuration to a dedicated board file.

Change-Id: I8d5dfecab2783f60b572180de71778c788c85483
Signed-off-by: Jin Hong <jinh@codeaurora.org>