GitLab

Featurizing card detection with CONFIG_MMC_MSM_CARD_HW_DETECTION
is not giving any benefit hence remove it.

Change-Id: I933de6c3979352d29b150cc061622c5b70075787
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

dfab_clk is used to vote for SDCC AHB clock derived
from Dayatona fabric. This naming convention is invalid
for targets where the AHB clocks are derived from other
buses like peripheral NoC. Hence, rename this to a generic
name that is applicable for all targets.

Change-Id: I9563342f07430cc000c86a93d265ff126003c8a5
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>

Typically eMMC card have IO voltage different than card VDD
voltage and specification names it as VCCQ voltage. Currently
driver refers regulator powering VCCQ as sdc_vccq.

UHS-I (Ultra High Speed) SD cards may also have the IO voltage
different then card VDD voltage and there is no specification
defined name for it so driver refers regulator powering this
SD card IO voltage as sdc_vddp.

But ultimately both are referring to regulators powering IO voltage
so it makes sense to refer both (sdc_vccq & sdc_vddp) as
sdc_vdd_io regulator. So this patch combines them as sdc_vdd_io
regulator.

CRs-Fixed: 369258
Change-Id: Ieafffbaebc9843c0b8683b87d2bada6b7666c142
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

If there is no voting for the system fabric clock, it may run at the
minimum clock speed. If system fabric is running at lower speed (than what
is needed by SDCC workload), SDCC read & write throughput numbers may be
degraded.

This patch adds the msm bus voting for bandwidth required by SDCC driver
based on card clock speed and bus width.

CRs-Fixed: 355327
Change-Id: I2542a3b9d2b9909d48304d52b3256ec607e433e2
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

To prevent speed degradation in high throughput
scenarios, specify CPU_DMA latency which gives
acceptable QOS. This should be derived without
knowledge of specific low power mode latencies.

For MMC/SD cards, reads tend to be the fastest
transactions, and suffer most from latency. To
ensure acceptable QOS, the average chunk size read
is used with typical best-in-class read speeds
seen across targets and cards.

With an average chunk size of 128KiB transferred
at 30MB/s, a 5% degradation in speed allows for
an additional 200us latency. This default can
be overridden by newer targets with more stringent
latency requirements.

Change-Id: I77d320d2b5e34e3b72ba41ed25454ece042eeddb
Signed-off-by: Oluwafemi Adeyemi <aadeyemi@codeaurora.org>

If SDIO slot is using the dedicated MSM pins rather than GPIO
pins then SDIO wakeup interrupt configuration would require
calling msm_mpm_* APIs. For such slots, let's indicate this
by setting a "mpm_sdiowakeup_int" platform entry to appropriate
MPM interrupt number. SDCC will use this entry to call
msm_mpm_* APIs when required.

Change-Id: I8fbeb9bd54c68f0285427d5754444818b66e6e4f
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

CONFIG_MMC_MSM_SDIO_SUPPORT config option was added
to indicate that host controller is capable of detecting
SDIO operational interrupt. But all the current SDCC
HW revisions support the SDIO operational interrupt
detection, this config option is going to be removed.
So this patch removes any code featurization using this
config.

Change-Id: I9768b5b8e089d4b1e57c09d6b364de6daf32e54d
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

During the SDCC DMA transfer, if DMA transfer time is
long enough to do IDLE power collapse then system may
go into IDLE power collapse and once SDCC DMA transfer
is completed, system wakes up from Idle Power Collapse
due to SDCC DMA interrupt. But delay for waking up
from Idle Power collapse could be as large as 5 ms which
really degrades the overall read & write throughputs
for SD/eMMC/SDIO cards.

For example, following are the performance numbers with
eMMC card on MSM8960 platform with and without Idle Power
Collapse.

Idle Power collapse enabled:
LMDD Read throughput = ~14 MB/s
LMDD Write throughput = ~6 MB/s

Idle Power Collapse disabled:
LMDD Read throughput = ~25 MB/s
LMDD Write throughput = ~8 MB/s

So this change votes against the Idle power collapse by registering
with PM QOS about it's acceptable DMA latency when SDCC transfer is
active. This latency value is one more than the latency of SWFI
which means system can go into SWFI but not in any of the other
low power modes (including Idle power collapse).

Change-Id: I2c8de5e9b4204468f9166aea7bcdee5b70ed62b1
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>

Move the MSM9615 SDCC devices and initialization code into a
dedicated board file.

Change-Id: I2049843f350bf49ac25f1da298240104d79a76e2
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Remove the MSM / APQ prefixes from 8930, 8960, and 8064
board files.

Change-Id: I8368be0b80385a40616fa2fcd2f108df66faf6ee
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

Move the APQ8064 SDCC devices and initialization code into
a dedicated board file.

Change-Id: I2f45d453954d6241e3ba11b0290d318a19f8159d
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

Move the MSM8960 SDCC devices and initialization code into
a dedicated board file.

Change-Id: Ia504c5423d7ff1b85cf076aa4b0695d7a65d0c70
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>