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The dynamic UUC algorithm changes the UUC as load, state of charge and
temperature changes. This uncontrolled behaviour causes unacceptable
jumps in state of charge numbers.

Replace the dynamic UUC algorithm with a simple average current based
UUC. The average current is calculated by remembering the load for last
few (16) samples. Also to maintain a reasonable UUC while charging, a
load of 300mA is assumed.

Note that the first time UUC is calculated we don't have load samples
and in that case the instantaneous current is used.

Since we now don't change the UUC with respect to max possible load
(itest), the usage of this value is removed.  Also instead of failure
voltage we introduce cutoff voltage which represents the loaded voltage
by which the battery should be reported 0%.

Change-Id: Ia640164ee2c9690537308d4e840953824ba15b58
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Experiments have shown that shutdown_soc is very accurate. However
upon a restart, the battery may be unsettled, leading to a significantly
different power on soc.

Update the code to force the value of shutdown soc on the power on
soc. To do this simply update the power on OCV (open circuit voltage)
value.

Change-Id: I1015b800e559cb08422364ffc8c8b981ddd4f07e
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

The power supply api reports usb as missing if a usb wall charger
is plugged in - this is expected as a usb wall charger should be
treated as a dc charger - not a usb charger.

The bms needs to know if anything is connected to the usb port, it
does not care whether it is a usb wall charger or pc usb charger.

Use a direct api exposed by the charger that reports the USBIN_VALID
bit.

Change-Id: Ide05f7da1b14ad3b288633e887611dd5fa79276a
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Introduce periodic hkadc calibration again. A bug was introduced when
periodic ccadc calibration code was moved to the ccadc driver - hkadc
calibration got dropped.

Reintroduce periodic hkadc calibration.

Change-Id: Ib22e03ce881320ca556bfbddd55e658b42363065
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

There is a bug in the sequence between when the calibration work is
scheduled and the global chip pointer is initialized. If work is
scheduled before the chip pointer is initialized it refuses to
calibrate.

Initialize the chip pointer before scheduling calibration work.

Change-Id: I333c97c005e8bc17a28fc0dac3f76e4f26fcc486
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

The code is rounding down state of charge value in the final step of the
calculation. Instead use a division that returns the closest integer.

Change-Id: Ia47d1c4eb684dd4c31e454dc762add0feab66b75
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Since battery resistance is found to be changing w.r.t. state of charge,
temperature and time since a load change happened, it is best if rbatt
is estimated using learnt tables.

Remove all the code that attempts to read battery resistance from BMS.

Change-Id: Id8d84d610df0bcca79d7e42ffae572c0898d63c6
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

If the battery fet is open, the current sourced or sinked from the
battery is very low. There is a high chance that an open circuit
voltage(OCV) happens. Putting the BMS in override mode resets the timer
whose expiry causes an OCV.

Avoid putting the BMS in override mode if battery fet is open.

Change-Id: Idc463bcc55b51cf188cc8ee440a66f763654f174
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>

Required by 8x30 platform

Change-Id: I51b39e1ee5e367fd72151854e3d421538074d6d6
Signed-off-by: Wentao Xu <wentaox@codeaurora.org>

Enable content protection by setting CONFIG_MSM_VIDC_CONTENT_PROTECTION in
target config file

Change-Id: I8e9b43b6eb09a11c0b5d987903b8bbffde1572e3
Signed-off-by: Riaz Ur Rahaman <riazr@codeaurora.org>

* changes:
  msm: pil-q6v5: Update clock calls to fix MSS PIL with full bootchain
  msm: clock-8974: Add clock to allow MSS to access memory

Maximum allowed size of BAM descriptor is 32K-1, the size
allocated by demux was changed accordingly. Notifications
from TSPP driver is set based on number of descriptors and
not on number of bytes.

TSIF buffer was enlarged to cope with 80Mbit/sec streams

Change-Id: Ic9a9f0a5144293ac30e5548bbbb4d284d72c3a9e
Signed-off-by: Hamad Kadmany <hkadmany@codeaurora.org>

LPASS and MSS have different requirements related to the order that
their clocks are enable/disabled and resets are asserted/de-asserted.
Currently, this causes 'clock stuck off' warnings in the kernel logs
when MSS is booted multiple times.

Fix this by reordering the MSS clock calls so that the core_clk reset
is de-asserted prior to enabling its iface_clk. Because doing this
would break LPASS (which requires iface_clk to be on for the core_clk
reset de-assertion to work), we are forced to separate the MSS and
LPASS clock sequences into separate functions and move them into their
respective PIL files.

MSS PIL also requires an additional clock that is added as part of
this fixup. The gcc_mss_q6_bimc_axi_clk is needed for the MSS Q6
to access memory.

Change-Id: Id877781f201a7267f72b52045ed2b87ebf7b4e05
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The MSS subsystem needs the gcc_mss_q6_bimc_axi_clk to be turned
on to allow the modem Q6 to access DDR. Add support for this
clock.

Change-Id: I2fe0d8740143d8f18eb5c8770bc4c4b07339c060
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>

* changes:
  msm: pil-q6v5-lpass: Enable lpass_q6_axi_clk
  msm: clock-8974: Add lpass_q6_axi_clk for PIL
  msm: clock-8974: Switch slimbus core clock frequency to 24.576 MHz.
  msm: platsmp: Support the full boot chain for 8974
  Revert "msm: clock-8974: Set GCC_BOOT_CLOCK_* registers to not force-on clocks"

This clock must be enabled for the LPASS Q6 to access the memory
from which it will execute.

Change-Id: I1bdd4d8fb32d85c28296de3827f70505be7ee70e
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

The PIL driver needs to enable a clock required by the
LPASS subsystem. Add support for this clock.

Change-Id: I38ecf1ce84939967b633b0ef37b764893ec19252
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>

The slimbus driver needs a frequency of 24.576 MHz from their
core clock.

Change-Id: Ic978bfb47f944778613954db12d7b373b7e8751f
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>

With the full boot chain, the secondary CPUs are held in
reset until the primary CPU explicitly releases them from
reset.

Change-Id: Ie2a9f235386133d570dc826fe1cf5b44587a0706
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

The GCC_BOOT_CLOCK_* register forces on certain USB and Krait
clocks. Clearing these registers is causing unclocked accesses
or possibly removing the clock from under the CPU. Temporarily
leave these registers alone.

This reverts commit fc3c55c6

.

Change-Id: I32e5dbcce94c931e1c56a42483e6cdeca479f055
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>

The FSM targets need to use the Watchdog1 timer instead of the
Watchdog0 timer. Add support to get the base and the interrupt
information from the platform data so that the watchdog driver
can support both WDT0 and WDT1.

Change-Id: Ibce013c0287e34dbd702d75dab2c3f321132e9ed
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>

Enable OCMEM power debug and OCMEM power control
disable mode until all power operations are verified with RPM.

Change-Id: I915ef53d1b84344f3cdef8f45f94eafa067b0172
Signed-off-by: Naveen Ramaraj <nramaraj@codeaurora.org>

When notify packet transfer failed, notify_count and cpkt_resp_q
would go out of sync. After the fix the packets are also removed from
the queue.

Change-Id: If33ea5070f460617179a77063a9e58c47ed93167
CRs-Fixed: 383661
Signed-off-by: Anna Perel <aperel@codeaurora.org>

The mentioned device data entries were defined earlier in a patch but
does not match the relevant documentation. In due course of merging/
auto-rebasing on the initial patch (that added these entries), the
changes in this file was replaced with the incorrect ones, which got
merged.

This patch corrects the entries as per the documentation by doing the
following:
  -Add reg-names to refer to the crypto register base and bam register
   base.
  -Rename "bam-pipes" to "bame-pipe-pair".

Change-Id: I47974b3c12500ca70ea46fcd58841af741461004
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>

This allows the clock selected for measurement to be observed
using test equipment attached to the PLL_TEST pin on the MSM.

Change-Id: I91384690e0979cbd51d5fe2ff417ceb711d01a11
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Add thermal monitoring and mitigation to kernel boot on msm8974
to prevent thermal conditions during boot time.

Change-Id: I9db10a4a69772fdcb8f2a450044ce446da8b593c
Signed-off-by: Eugene Seah <eseah@codeaurora.org>

* changes:
  coresight: implement stm hardware event and port enable sysfs nodes
  coresight: enable stm logging for ftrace events and printk
  coresight: implement coresight abort
  coresight: coresight tmc driver
  coresight: add coresight devices to msm8974 device tree