- 15 Aug, 2012 7 commits
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Abhijeet Dharmapurikar authored
When a strong battery is removed, it was seen that the battery voltage lines on the phone take about five to six seconds to go below 2.1volts where the pmic resets all the battery backed registers. If a new battery is plugged in within this time the driver will force the shutdown soc on this battery which is incorrect. Compare the shutdown soc with the calculated soc and if they are different than a configurable limit, simply discard the shutdown soc and use the calculated soc. Change-Id: I02e7c78eb5e9df0127ce7e78b0bd9792a8141039 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
The adjusting algorithm was designed to prevent uvlo event towards low state of charge situations. It works by decreasing ocv so that the a lower soc is reported. When the battery is fully charged, we fake an ocv event, causing the ocv to jump to 100% and cc to 0. But after a few milliseconds when charging stops, the adjusting algorithm reduces the ocv which causes the SOC to jump from 100% to 99%. This jump from 100 to 99 is incorrect. Moreover we have seen quick decreases at high soc range because of the adjusting algorithm. To fix that and the 100 to 99% jumps simply don't run the adjusting algorithm when the battery soc is above 90%. Change-Id: I68e8bb72ec0e58552f9fedecceaffbf149c1f10e Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
When ocv (open circuit voltage of the battery) is adjusted to match a specific soc, rbatt (the battery resistance) changes too. This is because rbatt is dependent on the remaining charge which changes as the ocv changes. The issue we observed with this changing rbatt was the unusable charge changes which causes the soc to move away from the soc the algorithm attempts to match. To get around this issue adjust both the rbatt and ocv in a iterative fashion until rbatt value stabilizes. Change-Id: Id3e36c1a8361a6d71b63fca3e6b0c2a4a9bb7e06 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
The soc (state of charge) calculation algorithms and the associated adjusting algorithms were coded assuming that the soc will be queried at distant intervals (more than 20 seconds). However this assumption is bad and soc can be queried at sub second intervals. These soc queries in quick succession causes the adjusting algorithm to over correct the battery voltage. Separate the soc calculation from the soc reporting - calculate soc at specific intervals, while the reporting uses the values resulting from the latest calculation. This way the adjusting algorithms run at specified intervals and are not perturbed by the sub second querying for soc. Change-Id: I240bfdbd3ae3b2e37ae16cc3757a25f5a918e972 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
When ocv (open circuit voltage of the battery) is adjusted to match a specific soc, rbatt (the battery resistance) changes too. This is because rbatt is dependent on the remaining charge which changes as the ocv changes. The issue we observed with this changing rbatt was the unusable charge changes which causes the soc to move away from the soc the algorithm attempts to match. To get around this issue adjust both the rbatt and ocv when we want to match a soc for a specific soc. Change-Id: Ifa8efe1e37b9982d6d67730f911e47e369e9b4ff Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
When the battery percent charge goes low we want to increase the frequency of state of charge updates. This helps the correction algorithm ample opportunities to correct the state of charge and prevent a low voltage shutdown. Change-Id: Ie846350ee4c1fd70198d28646779b20349134ef7 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
It could happen that the calculated soc was higher than the reported soc even when a charger is not plugged in. This usually happens when the battery temperature increases or the average current changes causing unusable charge to go low. The current code never reports this high soc unless a charger is plugged in. However at the instant when charger is plugged in, the driver reports that high calculated soc. This jump in soc in an instant is unacceptable. Slowly increase the reported soc so that it approaches the calculated soc while charging. Basically we are playing catchup between reported soc and calculated soc. The catch up time is based on how big the difference between calculated soc and reported soc is - we allow 60 seconds per percent delta. Change-Id: Ic1ae741c23ea596a46ca2cd49b58c75cf773c3e5 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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- 13 Aug, 2012 19 commits
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Abhijeet Dharmapurikar authored
The dynamic UUC algorithm changes the UUC as load, state of charge and temperature changes. This uncontrolled behaviour causes unacceptable jumps in state of charge numbers. Replace the dynamic UUC algorithm with a simple average current based UUC. The average current is calculated by remembering the load for last few (16) samples. Also to maintain a reasonable UUC while charging, a load of 300mA is assumed. Note that the first time UUC is calculated we don't have load samples and in that case the instantaneous current is used. Since we now don't change the UUC with respect to max possible load (itest), the usage of this value is removed. Also instead of failure voltage we introduce cutoff voltage which represents the loaded voltage by which the battery should be reported 0%. Change-Id: Ia640164ee2c9690537308d4e840953824ba15b58 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
Experiments have shown that shutdown_soc is very accurate. However upon a restart, the battery may be unsettled, leading to a significantly different power on soc. Update the code to force the value of shutdown soc on the power on soc. To do this simply update the power on OCV (open circuit voltage) value. Change-Id: I1015b800e559cb08422364ffc8c8b981ddd4f07e Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
The power supply api reports usb as missing if a usb wall charger is plugged in - this is expected as a usb wall charger should be treated as a dc charger - not a usb charger. The bms needs to know if anything is connected to the usb port, it does not care whether it is a usb wall charger or pc usb charger. Use a direct api exposed by the charger that reports the USBIN_VALID bit. Change-Id: Ide05f7da1b14ad3b288633e887611dd5fa79276a Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
Introduce periodic hkadc calibration again. A bug was introduced when periodic ccadc calibration code was moved to the ccadc driver - hkadc calibration got dropped. Reintroduce periodic hkadc calibration. Change-Id: Ib22e03ce881320ca556bfbddd55e658b42363065 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
There is a bug in the sequence between when the calibration work is scheduled and the global chip pointer is initialized. If work is scheduled before the chip pointer is initialized it refuses to calibrate. Initialize the chip pointer before scheduling calibration work. Change-Id: I333c97c005e8bc17a28fc0dac3f76e4f26fcc486 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
The code is rounding down state of charge value in the final step of the calculation. Instead use a division that returns the closest integer. Change-Id: Ia47d1c4eb684dd4c31e454dc762add0feab66b75 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
Since battery resistance is found to be changing w.r.t. state of charge, temperature and time since a load change happened, it is best if rbatt is estimated using learnt tables. Remove all the code that attempts to read battery resistance from BMS. Change-Id: Id8d84d610df0bcca79d7e42ffae572c0898d63c6 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Abhijeet Dharmapurikar authored
If the battery fet is open, the current sourced or sinked from the battery is very low. There is a high chance that an open circuit voltage(OCV) happens. Putting the BMS in override mode resets the timer whose expiry causes an OCV. Avoid putting the BMS in override mode if battery fet is open. Change-Id: Idc463bcc55b51cf188cc8ee440a66f763654f174 Signed-off-by:
Abhijeet Dharmapurikar <adharmap@codeaurora.org>
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Linux Build Service Account authored
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Linux Build Service Account authored
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Linux Build Service Account authored
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Wentao Xu authored
Required by 8x30 platform Change-Id: I51b39e1ee5e367fd72151854e3d421538074d6d6 Signed-off-by:
Wentao Xu <wentaox@codeaurora.org>
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Riaz Rahaman authored
Enable content protection by setting CONFIG_MSM_VIDC_CONTENT_PROTECTION in target config file Change-Id: I8e9b43b6eb09a11c0b5d987903b8bbffde1572e3 Signed-off-by:
Riaz Ur Rahaman <riazr@codeaurora.org>
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Linux Build Service Account authored
* changes: msm: pil-q6v5: Update clock calls to fix MSS PIL with full bootchain msm: clock-8974: Add clock to allow MSS to access memory
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Linux Build Service Account authored
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Linux Build Service Account authored
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Linux Build Service Account authored
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Hamad Kadmany authored
Maximum allowed size of BAM descriptor is 32K-1, the size allocated by demux was changed accordingly. Notifications from TSPP driver is set based on number of descriptors and not on number of bytes. TSIF buffer was enlarged to cope with 80Mbit/sec streams Change-Id: Ic9a9f0a5144293ac30e5548bbbb4d284d72c3a9e Signed-off-by:
Hamad Kadmany <hkadmany@codeaurora.org>
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Linux Build Service Account authored
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- 12 Aug, 2012 14 commits
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Matt Wagantall authored
LPASS and MSS have different requirements related to the order that their clocks are enable/disabled and resets are asserted/de-asserted. Currently, this causes 'clock stuck off' warnings in the kernel logs when MSS is booted multiple times. Fix this by reordering the MSS clock calls so that the core_clk reset is de-asserted prior to enabling its iface_clk. Because doing this would break LPASS (which requires iface_clk to be on for the core_clk reset de-assertion to work), we are forced to separate the MSS and LPASS clock sequences into separate functions and move them into their respective PIL files. MSS PIL also requires an additional clock that is added as part of this fixup. The gcc_mss_q6_bimc_axi_clk is needed for the MSS Q6 to access memory. Change-Id: Id877781f201a7267f72b52045ed2b87ebf7b4e05 Signed-off-by:
Matt Wagantall <mattw@codeaurora.org>
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Vikram Mulukutla authored
The MSS subsystem needs the gcc_mss_q6_bimc_axi_clk to be turned on to allow the modem Q6 to access DDR. Add support for this clock. Change-Id: I2fe0d8740143d8f18eb5c8770bc4c4b07339c060 Signed-off-by:
Vikram Mulukutla <markivx@codeaurora.org>
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Linux Build Service Account authored
* changes: msm: pil-q6v5-lpass: Enable lpass_q6_axi_clk msm: clock-8974: Add lpass_q6_axi_clk for PIL msm: clock-8974: Switch slimbus core clock frequency to 24.576 MHz. msm: platsmp: Support the full boot chain for 8974 Revert "msm: clock-8974: Set GCC_BOOT_CLOCK_* registers to not force-on clocks"
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Linux Build Service Account authored
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Linux Build Service Account authored
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Matt Wagantall authored
This clock must be enabled for the LPASS Q6 to access the memory from which it will execute. Change-Id: I1bdd4d8fb32d85c28296de3827f70505be7ee70e Signed-off-by:
Matt Wagantall <mattw@codeaurora.org>
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Vikram Mulukutla authored
The PIL driver needs to enable a clock required by the LPASS subsystem. Add support for this clock. Change-Id: I38ecf1ce84939967b633b0ef37b764893ec19252 Signed-off-by:
Vikram Mulukutla <markivx@codeaurora.org>
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Vikram Mulukutla authored
The slimbus driver needs a frequency of 24.576 MHz from their core clock. Change-Id: Ic978bfb47f944778613954db12d7b373b7e8751f Signed-off-by:
Vikram Mulukutla <markivx@codeaurora.org>
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Stepan Moskovchenko authored
With the full boot chain, the secondary CPUs are held in reset until the primary CPU explicitly releases them from reset. Change-Id: Ie2a9f235386133d570dc826fe1cf5b44587a0706 Signed-off-by:
Stepan Moskovchenko <stepanm@codeaurora.org>
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Stepan Moskovchenko authored
The GCC_BOOT_CLOCK_* register forces on certain USB and Krait clocks. Clearing these registers is causing unclocked accesses or possibly removing the clock from under the CPU. Temporarily leave these registers alone. This reverts commit fc3c55c6 . Change-Id: I32e5dbcce94c931e1c56a42483e6cdeca479f055 Signed-off-by:
Stepan Moskovchenko <stepanm@codeaurora.org>
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Rohit Vaswani authored
The FSM targets need to use the Watchdog1 timer instead of the Watchdog0 timer. Add support to get the base and the interrupt information from the platform data so that the watchdog driver can support both WDT0 and WDT1. Change-Id: Ibce013c0287e34dbd702d75dab2c3f321132e9ed Signed-off-by:
Rohit Vaswani <rvaswani@codeaurora.org>
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Naveen Ramaraj authored
Enable OCMEM power debug and OCMEM power control disable mode until all power operations are verified with RPM. Change-Id: I915ef53d1b84344f3cdef8f45f94eafa067b0172 Signed-off-by:
Naveen Ramaraj <nramaraj@codeaurora.org>
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Linux Build Service Account authored
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Anna Perel authored
When notify packet transfer failed, notify_count and cpkt_resp_q would go out of sync. After the fix the packets are also removed from the queue. Change-Id: If33ea5070f460617179a77063a9e58c47ed93167 CRs-Fixed: 383661 Signed-off-by:
Anna Perel <aperel@codeaurora.org>
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